Abstract
This paper presents the design of a voice acqui-sition and recognition system in VHDL, mainly optimized for FPGA DE1-SoC. The system implements advanced digital signal processing techniques combined with classification through the K-Nearest Neighbors (KNN) algorithm. The system operates at a 320 kHz sampling rate, with a latency of 10 ns and power consumption of 1.2 W. The design enhances precision and noise rejection through the use of Hamming windows and integer-based processing. Future improvements will focus on the implementation of neural networks to replace the KNN algorithm and further increase system accuracy.
| Original language | American English |
|---|---|
| Title of host publication | Proceedings of the 2024 IEEE 31st International Conference on Electronics, Electrical Engineering and Computing, INTERCON 2024 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9798350378344 |
| DOIs | |
| State | Indexed - 2024 |
| Externally published | Yes |
| Event | 31st IEEE International Conference on Electronics, Electrical Engineering and Computing, INTERCON 2024 - Lima, Peru Duration: 6 Nov 2024 → 8 Nov 2024 |
Publication series
| Name | Proceedings of the 2024 IEEE 31st International Conference on Electronics, Electrical Engineering and Computing, INTERCON 2024 |
|---|
Conference
| Conference | 31st IEEE International Conference on Electronics, Electrical Engineering and Computing, INTERCON 2024 |
|---|---|
| Country/Territory | Peru |
| City | Lima |
| Period | 6/11/24 → 8/11/24 |
Bibliographical note
Publisher Copyright:© 2024 IEEE.
Keywords
- DE1-SoC
- Digital Signal Processing
- FPGA
- K-Nearest Neighbors (KNN)
- VHDL
- Voice Recognition
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